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HC705JB2GRS/H Datasheet(PDF) 15 Page - NXP Semiconductors |
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HC705JB2GRS/H Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 128 page  August 28, 1998 GENERAL RELEASE SPECIFICATION GENERAL DESCRIPTION REV 1.1 1-3 1.3 MCU STRUCTURE Figure 1-1 shows the block diagram of the MC68HC705JB2. Figure 1-1. MC68HC705JB2 Block Diagram 128 Bytes RAM 2048 Bytes EPROM Low Speed USB 16-bit Timer Core TImer OSC ÷2 RESET and IRQ LVR VREF POWER SUPPLY CPU CONTROL ALU 68HC05 CPU ACCUM INDEX REG. CPU REGISTERS PROGRAM COUNTER COND CODE REG. 0 0 0 0 000 11 STK PNTR 0 111H I N Z C PA0x PA1x PA2x PA3x PA4y PA5y PA6y PA7y PB0 PB1 PB2 VDD VSS 3.3V RESET IRQ TCAP D+ D– OSC1 OSC2 y: 8 mA current sink capability : 25 mA current sink, open-drained x: External edge interrupt capability, with internal pullup, slow transition O/P : TCAP is shared with PB0 with Schmitt trigger input Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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