HC705JB2GRSSLASHH datasheet(49/128 Pages) NXP

49 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

INPUT/OUTPUT PORTS

REV 1.1

7-3

7.1.3 Port A Pulldown Register

All Port A I/O pins may have software programmable pulldown devices enabled by

a mask option. If the pulldown/up mask option is selected, the pulldown is

activated whenever the corresponding bit in the PDURA is clear. If the

corresponding bit in the PDURA bit is set or the mask option for pulldown is not

chosen, the pulldown will be disabled. A pulldown on an I/O pin is activated only if

the I/O pin is programmed as an input.

The PDURA is a write-only register. Any reads of location $0010 will return

undeﬁned results. Since reset clears both the DDRA and the PDURA, all pins will

initialize as inputs with the pulldown active (if enabled by mask option).

7.1.4 Port A Drive Capability

The outputs of the PA4, PA5, PA6 and PA7 are capable of sinking 8 mA (typical) of

current to VSS.

7.1.5 Port A I/O Pin Interrupts

The inputs to PA0, PA1, PA2, PA3 may be connected to the IRQ input of the CPU

if enabled by a mask option. PA0 to PA4 also has a Schmitt trigger circuit

implemented as part of its input circuitry.

When connected as an alternate source of an IRQ interrupt, PA0-3 input pins will

behave the same as the IRQ pin itself, except that their active state is a logical one

or a rising edge. The IRQ pin has an active state that is a logical zero or a falling

edge.

If the mask option for edge-and-level trigger sensitivity interrupts are chosen, the

presence of a logic one or occurrence of a rising edge on any one of the lower four

Port A pins will cause an IRQ interrupt request. If the edge-only sensitivity is

selected, the occurrence of a rising edge on any one of the lower four Port A pins

will cause an IRQ interrupt request. As long as any one of the lower four Port A

IRQ inputs remains at a logic one level, the other of the lower four Port A IRQ

inputs are effectively ignored.

NOTE

The BIH and BIL instructions will only apply to the level on the IRQ

pin itself, and not to the internal IRQ input to the CPU. Therefore BIH

and BIL cannot be used to test the state of the lower four Port A

input pins as a group.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H Datasheet(PDF) 49 Page - NXP Semiconductors