HC705JB2GRSSLASHH datasheet(48/128 Pages) NXP

48 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

INPUT/OUTPUT PORTS

MC68HC705JB2

7-2

REV 1.1

7.1

PORT A

Port A is an 8-bit bidirectional port which shares four of its pins with the IRQ

interrupt system as shown in Figure 7-1. Each Port A pin is controlled by the

corresponding bits in a data direction register, a data register, and a pulldown

Direction Register (DDRA) is located at address $0004. The Port A Pulldown

PDURA. The Port A Data Register is unaffected by reset.

Figure 7-1. Port A I/O Circuitry

7.1.1 Port A Data Register

Each Port A I/O pin has a corresponding bit in the Port A Data Register. When a

Port A pin is programmed as an output the state of the corresponding data

programmed as an input, any read of the Port A Data Register will return the logic

state of the corresponding I/O pin. The Port A data register is unaffected by reset.

7.1.2 Port A Data Direction Register

Each Port A I/O pin may be programmed as an input by clearing the

corresponding bit in the DDRA, or programmed as an output by setting the

corresponding bit in the DDRA. The DDRA can be accessed at address $0004.

The DDRA is cleared by reset.

Write $0010

100

µA

Pulldown

Read $0000

Write $0000

Read $0004

Data

PA0-PA3 only: to IRQ

interrupt system

8 mA Sink

Capability

(Bits 4-7 Only)

Output

Mask Option

(Software Pulldown Inhibit)

Internal HC05

Data Bus

Reset

(RST)

Write $0004

Data Direction

Pulldown

Note: each I/O port pin can have pulldown device

I/O Pin

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H Datasheet(PDF) 48 Page - NXP Semiconductors

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