HC705JB2GRSSLASHH datasheet(4/128 Pages) NXP

4 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

MC68HC705JB2

REV 1.1

TABLE OF CONTENTS

Section

Title

Page

4.4.1

External Interrupt (IRQ) ............................................................................... 4-4

4.4.2

IRQ Control/status Register (ICSR) $0A ..................................................... 4-5

4.4.3

Optional External Interrupts (PA0-PA3)....................................................... 4-6

4.4.4

Timer1 Interrupt (TIMER1)........................................................................... 4-7

4.4.5

USB Interrupt (USB) .................................................................................... 4-7

4.4.6

MFT Interrupt (MFT) .................................................................................... 4-7

SECTION 5

RESETS

5.1

EXTERNAL RESET (RESET).......................................................................... 5-2

5.2

INTERNAL RESETS ........................................................................................ 5-2

5.2.1

Power-On Reset (POR) ............................................................................... 5-2

5.2.2

USB Reset ................................................................................................... 5-2

5.2.3

Illegal Address Reset (ILADR)..................................................................... 5-3

5.2.4

Low Voltage Reset (LVR) ............................................................................ 5-3

SECTION 6

LOW POWER MODES

6.1

STOP MODE.................................................................................................... 6-1

6.2

WAIT MODE .................................................................................................... 6-1

6.3

DATA-RETENTION MODE.............................................................................. 6-3

SECTION 7

INPUT/OUTPUT PORTS

7.1

PORT A............................................................................................................ 7-2

7.1.1

Port A Data Register.................................................................................... 7-2

7.1.2

Port A Data Direction Register..................................................................... 7-2

7.1.3

Port A Pulldown Register............................................................................. 7-3

7.1.4

Port A Drive Capability................................................................................. 7-3

7.1.5

Port A I/O Pin Interrupts............................................................................... 7-3

7.2

PORT B............................................................................................................ 7-4

7.2.1

Port B Data Register.................................................................................... 7-4

7.2.2

Port B Data Direction Register..................................................................... 7-5

7.2.3

Slow Output Falling-Edge Transition ........................................................... 7-5

7.2.4

Port B Pulldown/Pullup Register.................................................................. 7-5

7.3

I/O PORT PROGRAMMING ............................................................................ 7-6

7.3.1

Pin Data Direction........................................................................................ 7-6

7.3.2

Output Pin.................................................................................................... 7-6

7.3.3

Input Pin....................................................................................................... 7-6

7.3.4

I/O Pin Transitions ....................................................................................... 7-7

7.3.5

I/O Pin Truth Tables..................................................................................... 7-7

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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