HC705JB2GRSSLASHH datasheet(35/128 Pages) NXP

35 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

INTERRUPTS

REV 1.1

4-5

The IRQ pin is one source of an IRQ interrupt and a mask option can also enable

the four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources.

Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes

from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on

any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled. If "edge-only"

sensitivity is chosen by a mask option, only the IRQ latch output can activate an

IRQF ﬂag which creates a request to the CPU to generate the IRQ interrupt

sequence. This makes the IRQ interrupt sensitive to the following cases:

•

Falling edge on the IRQ pin.

•

Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).

If level sensitivity is chosen, the active high state the signal to the clock input of

the IRQ latch can also activate an IRQF ﬂag which creates an IRQ request to the

CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt

sensitive to the following cases:

•

Low level on the IRQ pin.

•

Falling edge on the IRQ pin.

•

High level on any PA0- PA3 pin with IRQ enabled (via mask option).

•

Rising edge on any PA0- PA3 pin with IRQ enabled (via mask option).

The IRQE enable bit controls whether an active IRQF ﬂag can generate an IRQ

interrupt sequence. This interrupt is serviced by the interrupt service routine

located at the address speciﬁed by the contents of $1FFA and $1FFB.

The IRQ latch is automatically cleared by entering the interrupt service routine IF

IRQE enable bit is cleared. If IRQE enable bit is also set, the only way of clearing

IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one to

the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF ﬂag. As

long as the output state of the IRQF ﬂag bit is active the CPU will continuously re-

enter the IRQ interrupt sequence until the active state is removed or the IRQE

enable bit is cleared.

4.4.2 IRQ Control/status Register (ICSR) $0A

The IRQ interrupt function is controlled by the ICSR located at $000A. All unused

bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is

set by reset.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ICSR

IRQE

IRQF

$000A

IRQR

reset:

10000000

Figure 4-3. IRQ Control and Status Register (ICSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H Datasheet(PDF) 35 Page - NXP Semiconductors

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