HC705JB2GRSSLASHH datasheet(58/128 Pages) NXP

58 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

MULTI-FUNCTION TIMER

MC68HC705JB2

8-4

REV 1.1

TOFR - Timer Overﬂow Acknowledge

The TOFR is an acknowledge bit that resets the TOF ﬂag bit. This bit is

unaffected by reset. Reading the TOFR will always return a logical zero.

1 =

Clears the TOF ﬂag bit.

0 =

Does not clear the TOF ﬂag bit.

RTIFR - Real Time Interrupt Acknowledge

The RTIFR is an acknowledge bit that resets the RTIF ﬂag bit. This bit is

unaffected by reset. Reading the RTIFR will always return a logical zero.

1 =

Clears the RTIF ﬂag bit.

0 =

Does not clear the RTIF ﬂag bit.

RT1, RT0 - Real Time Interrupt period select bits

These two bits select one of the four real time interrupt periods.

8.2

OPERATION DURING STOP MODE

When STOP is exited by an external interrupt or an LVR reset or an external

RESET, the internal oscillator will resume, followed by a 128 or 4064 internal

processor oscillator stabilization delay.

Bus Frequency, fBUS=fOP=3.0 MHz

RT1

RT0

Divide Ratio

RTI Rate

214

5.46ms

215

10.92ms

216

21.85ms

217

43.69ms

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H Datasheet(PDF) 58 Page - NXP Semiconductors

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