HC705JB2GRSSLASHH datasheet(55/128 Pages) NXP

55 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

MULTI-FUNCTION TIMER

REV 1.1

8-1

SECTION 8

MULTI-FUNCTION TIMER

The MC68HC705JB2 core timer is a multi-function ripple counter. The features

include Timer Over Flow (TOF) and Power-On Reset (POR).

Figure 8-1. Multi-Function Timer Block Diagram

As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by

four (

÷4). NTF1 has the same phase and frequency as the processor bus clock,

PH2, but is not stopped by the WAIT Modes. This signal drives an 8-bit ripple

counter. The value of this 8-bit ripple counter can be read by the CPU at any time

by accessing the Timer Counter Register (TCNT) at address $09. A timer overﬂow

RTI Select Circuit

Overflow

Circuit

Detect

fOP÷2

÷210

Internal

Timer Clock

(NTF1)

TOF

RTIF

TOFE

RTIE

RT1

RT0

RTIFR

TOFR

Timer Control & Status Register ($08)

Timer Counter Register ($09)

Interrupt Circuit

7-bit counter

MCU Internal Bus

To CPU interrupt

÷214

÷215

÷217 ÷216

÷4

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H Datasheet(PDF) 55 Page - NXP Semiconductors

HC705JB2GRS/H Datasheet(HTML) 55 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL