HC705JB2GRSSLASHH datasheet(31/128 Pages) NXP

31 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

INTERRUPTS

REV 1.1

4-1

SECTION 4

INTERRUPTS

The MCU can be interrupted in six different ways:

•

Non-maskable Software Interrupt Instruction (SWI)

•

External Interrupt (IRQ)

•

Optional External Interrupt via IRQ on PA0-PA3 (mask option)

•

USB Interrupt

•

Timer1 Interrupt (16-bit Timer)

•

Multi-Function Timer Interrupt

4.1

CPU INTERRUPT PROCESSING

Interrupts cause the processor to save register contents on the stack and to set

the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware

interrupts do not cause the current instruction execution to be halted, but are

considered pending until the current instruction is complete.

If interrupts are not masked (I-bit in the CCR is clear) and the corresponding

interrupt enable bit is set the processor will proceed with interrupt processing.

Otherwise, the next instruction is fetched and executed. If an interrupt occurs the

processor completes the current instruction, then stacks the current CPU register

states, sets the I-bit to inhibit further interrupts, and ﬁnally checks the pending

hardware interrupts. If more than one interrupt is pending following the stacking

operation, the interrupt with the highest vector location shown in Table 4-1 will be

serviced ﬁrst. The SWI is executed the same as any other instruction, regardless

of the I-bit state.

When an interrupt is to be processed the CPU fetches the address of the

appropriate interrupt software service routine from the vector table at locations

$1FF4 to $1FFF as deﬁned in Table 4-1.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H Datasheet(PDF) 31 Page - NXP Semiconductors