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HC705JJ7GRS/D Datasheet(PDF) 127 Page - NXP Semiconductors

Part # HC705JJ7GRS/D
Description  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705JJ7GRS/D Datasheet(HTML) 127 Page - NXP Semiconductors

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Analog Subsystem
A/D Conversion Methods
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
Figure 8-11. A/D Conversion — OCF/ICF Control (Mode 3)
tDIS
(MIN)
tCHG x ICHG
CEXT
tCHG
tDIS
VX =
VMAX
CHG
COMP2
0
TOF
OCF
ICF
(MIN)
VCAP
tDIS
VX
1
2
3
1
2
(TCAP)
Point
Action
Software/Hardware Action
Dependent Variable(s)
0
Begin initial discharge and select mode
3 by clearing CHG and setting ATD2
and ATD1 in the ACR. Also set ICEN
bit in ACR and IEDG bit in TCR.
Software write
Software
1
VCAP falls to VSS. Set timer output
compare registers (OCRH and OCRL)
to desired charge start time.
Wait out minimum tDIS time.
Software write to OCRH, OCRL.
VMAX, IDIS, CEXT,
software
2
Stop discharge and begin charge when
the next OCF sets the CHG control bit
in ACR.
Timer OCF sets the CHG control
bit in the ACR.
Free-running timer
output compare, fOSC
3
VCAP rises to VX and comparator 2
output trips, setting CPF2 and CMP2,
which causes an ICF from the timer
and clears the CHG control bit in ACR.
Must clear CPF2 in order to trap next
CPF2 flag. Load next OCF.
Wait out tCHG time.
Timer ICF clears the CHG
control bit in the ACR.
VX, ICHG, CEXT
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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