HC705JJ7GRSSLASHD datasheet(50/230 Pages) NXP

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Interrupts

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Interrupts

4.5 Software Interrupt

The software interrupt (SWI) instruction causes a non-maskable

interrupt.

4.6 External Interrupts

These sources can generate external interrupts:

•

IRQ/VPP pin

•

PA3–PA0 pins

Setting the I bit in the condition code register or clearing the IRQE bit in

the interrupt status and control register disables these external

interrupts.

4.6.1 IRQ/VPP Pin

An interrupt signal on the IRQ/VPP pin latches an external interrupt

request. To help clean up slow edges, the input from the IRQ/VPP pin is

processed by a Schmitt trigger gate. When the CPU completes its

current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU

then tests the I bit in the condition code register and the IRQE bit in the

IRQ status and control register (ISCR). If the I bit is clear and the IRQE

bit is set, then the CPU begins the interrupt sequence. The CPU clears

the IRQ latch while it fetches the interrupt vector, so that another

external interrupt request can be latched during the interrupt service

routine. As soon as the I bit is cleared during the return from interrupt,

the CPU can recognize the new interrupt request. Figure 4-3 shows the

logic for external interrupts.

NOTE:

If the IRQ/VPP pin is not in use, it should be connected to the VDD pin.

The IRQ/VPP pin can be negative edge-triggered only or negative edge-

and low level-triggered. External interrupt sensitivity is programmed with

the LEVEL bit in the mask option register (MOR).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Datasheet(PDF) 50 Page - NXP Semiconductors