HC705JJ7GRSSLASHD datasheet(37/230 Pages) NXP

Part #	HC705JJ7GRS/D

Description	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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37 / 230 page

Memory

EPROM

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Memory

2.7 EPROM

The EPROM is located in two areas of the memory map:

•

Addresses $0700–$1EFF contain 6144 bytes of user EPROM.

•

Addresses $1FF0–$1FFF contain 16 bytes of EPROM reserved

for user vectors and COP and security register, and the mask

option register.

2.8 COP Register

As shown in Figure 2-6, a register location is provided at $1FF0 to set

the EPROM security1, select the optional features, and reset the COP

watchdog timer. The OPT bit controls the function of the PB4 port pin

and the availability to add an offset to any measured analog voltages.

See 8.5 Analog Status Register for more information

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the EPROM/OTPROM difficult for unauthorized users.

$1FF0

Bit 7

54321

Bit 0

Read:

EPMSEC

OPT

Write:

COPC

= Unimplemented

Figure 2-6. COP and Security Register (COPR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Datasheet(PDF) 37 Page - NXP Semiconductors