HC705JJ7GRSSLASHD datasheet(42/230 Pages) NXP

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Central Processor Unit (CPU)

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Central Processor Unit (CPU)

3.6 Program Counter (PC)

The program counter is a 16-bit register that contains the address of the

next instruction or operand to be fetched as shown in Figure 3-5. The

three most significant bits of the program counter are ignored internally

and appear as 111 during stacking and subroutine calls.

Normally, the address in the program counter automatically increments

to the next sequential memory location every time an instruction or

operand is fetched. Jump, branch, and interrupt operations load the

program counter with an address other than that of the next sequential

location.

3.7 Condition Code Register (CCR)

The condition code register is an 8-bit register whose three most

significant bits are permanently fixed at 111 as shown in Figure 3-6. The

condition code register contains the interrupt mask and four flags that

indicate the results of the instruction just executed. The following

paragraphs describe the functions of the condition code register.

Bit

Read:

Write:

Reset:

Loaded with Vector from $1FFE and $1FFF

Figure 3-5. Program Counter (PC)

Bit 7

654321

Bit 0

Read:

111

Write:

Reset:

1U1U

U = Unaffected

Figure 3-6. Condition Code Register (CCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Datasheet(PDF) 42 Page - NXP Semiconductors