HC705JJ7GRSSLASHD datasheet(79/230 Pages) NXP

Part #	HC705JJ7GRS/D

Description	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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79 / 230 page

Parallel Input/Output

Port A

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

7.3.1 Port A Data Register (PORTA)

The port A data register contains a bit for each of the port A pins. When

a port A pin is programmed to be an output, the state of its data register

bit determines the state of the output pin. When a port A pin is

programmed to be an input, reading the port A data register returns the

logic state of the pin. The upper two bits of the port A data register will

always read as logical zeros.

PA5–PA0 — Port A Data Bits

These read/write bits are software programmable. Data direction of

each bit is under the control of the corresponding bit in the port A data

direction register (DDRA). Reset has no effect on port A data.

$0000

Bit 7

654321

Bit 0

Read:

PA5

PA4

PA3

PA2

PA1

PA0

Write:

Reset:

Unaffected by Reset

Alternate:

KYBD3

KYBD2

KYBD1

KYBD0

= Unimplemented

Figure 7-1. Port A Data Register (PORTA)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Datasheet(PDF) 79 Page - NXP Semiconductors