HC705JJ7GRSSLASHD datasheet(63/230 Pages) NXP

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Resets

Internal Resets

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Resets

EPMSEC — EPROM Security1

The EPMSEC bit is a write-only security bit to protect the contents of

the user EPROM code stored in locations $0700–$1FFF.

OPT — Optional Features

The OPT bit enables two additional features: direct drive by

comparator 1 output to PB4; and voltage offset capability to sample

capacitor in analog subsystem.

1 = Optional features enabled

0 = Optional features disabled

COPC — COP Clear

COPC is a write-only bit. Periodically writing a logic zero to COPC

prevents the COP watchdog from resetting the MCU. Reset clears the

COPC bit.

1 = No effect on COP watchdog timer

0 = Reset COP watchdog timer

The COP watchdog reset will assert the pulldown device to pull the

RESET pin low for three to four cycles of the internal bus.

The COP watchdog reset function can be enabled or disabled by

programming the COPEN bit in the MOR.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the EPROM/OTPROM difficult for unauthorized users.

$1FF0

Bit 7

654321

Bit 0

Read:

EPMSEC

OPT

Write:

COPC

Reset:

UUUUUUU

= Unimplemented

U = Unaffected

Figure 5-2. COP and Security Register (COPR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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