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HC705JJ7GRS/D Datasheet(PDF) 83 Page - NXP Semiconductors |
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HC705JJ7GRS/D Datasheet(HTML) 83 Page - NXP Semiconductors |
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83 / 230 page  Parallel Input/Output Port A MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Parallel Input/Output Figure 7-4. Port A I/O Circuit PAx EXTERNAL INTERRUPT REQUEST PORT A DATA REGISTER BIT PAx READ $0004 WRITE $0000 READ $0000 WRITE $0010 PULLDOWN DEVICE RESET HIGH SINK/SOURCE CURRENT WRITE $0004 DATA DIRECTION REGISTER A BIT DDRAx PULLDOWN REGISTER A BIT PDIAx R R MASK OPTION REGISTER ($1FF1) CAPABILITY (PA0:3) Table 7-1. Port A Pin Functions Port A Pin(s) SWPDI (in MOR) Port A PORTA Access (Pin or Data Register) Result on Port A Pins PDIAx DDRAx* Read Write Pulldown Pin PA0 PA1 PA2 PA3 PA4 PA5 0 0 0 Pin Data On PAx In 0 1 0 Pin Data Off PAx In 1 X 0 Pin Data Off PAx In X X 1 Data Data Off PAx Out * DDRA can always be read or written. X = Don’t care Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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