HC705JJ7GRSSLASHD datasheet(58/230 Pages) NXP

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Interrupts

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Interrupts

4.10 Analog Interrupts

The analog subsystem can generate the following interrupts:

•

Voltage on positive input of comparator 1 is greater than the

voltage on the negative input of comparator 1

•

Voltage on positive input of comparator 2 is greater than the

voltage on the negative input of comparator 2

•

Trigger of the input capture interrupt from the programmable timer

as described in 4.8.1 Input Capture Interrupt.

Setting the I bit in the condition code register disables analog subsystem

interrupts. The controls for these interrupts are in the analog subsystem

control register (ACR) located at $001D, and the status bits are in the

analog subsystem status register (ASR) located at $001E.

4.10.1 Comparator Input Match Interrupt

A comparator input match interrupt occurs if either compare flag bit

(CPF1 or CPF2) in the ASR becomes set while the comparator interrupt

enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits

can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits

in the ASR. Reset clears these bits.

4.10.2 Input Capture Interrupt

The analog subsystem can also generate an input capture interrupt

through the 16-bit programmable timer. The input capture can be

triggered when there is a match in the input conditions for the voltage

comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the

input capture enable (ICEN) in the ACR is set, then an input capture will

be performed by the programmable timer. If the ICIE enable bit in the

TCR is also set, then an input compare interrupt will occur. Reset clears

these bits.

NOTE:

For the analog subsystem to generate an interrupt using the input

capture function of the programmable timer, the ICEN enable bit in the

ACR, and the ICIE and IEDG bits in the TCR must all be set.

Freescale Semiconductor, Inc.

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