HC705JJ7GRSSLASHD datasheet(47/230 Pages) NXP

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Interrupts

Interrupt Vectors

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Interrupts

NOTE:

If more than one interrupt request is pending, the CPU fetches the vector

of the higher priority interrupt first. A higher priority interrupt does not

actually interrupt a lower priority interrupt service routine unless the

lower priority interrupt service routine clears the I bit.

Table 4-1. Reset/Interrupt Vector Addresses

Function

Source

MOR

Control

Bit

Global

Hardware

Mask

Local

Software

Mask

Priority

(1 = Highest)

Vector

Address

Reset

Power-On Logic

RESET Pin

Low-Voltage Reset

Illegal Address Reset

—

$1FFE–$1FFF

COP Watchdog

COPEN1

Software

Interrupt

(SWI)

User Code

—

Same Priority

As Instruction

$1FFC–$1FFD

External

Interrupt (IRQ)

IRQ/VPP Pin

—

I Bit

IRQE Bit

$1FFA–$1FFB

PA3 Pin

PA2 Pin

PA1 Pin

PA0 Pin

PIRQ2

Core Timer

Interrupts

TOF Bit

RTIF Bit

—

I Bit

TOFE Bit

RTIE Bit

$1FF8–$1FF9

Programmable

Timer

Interrupts

ICF Bit

OCF Bit

TOF Bit

—

I Bit

ICIE Bit

OCIE Bit

TOIE Bit

$1FF6–$1FF7

Serial

Interrupt

SPIF Bit

—

I Bit

SPIE Bit

$1FF4–$1FF5

Analog

Interrupt

CPF1 Bit

CPF2 Bit

—

I Bit

CPIE Bit

$1FF2–$1FF3

NOTES:

1. COPEN enables the COP watchdog timer.

2. PIRQ enables port A external interrupts on PA0–PA3.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Datasheet(PDF) 47 Page - NXP Semiconductors

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