ZAMC4100GA2R datasheet(113/156 Pages) RENESAS

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ZAMC4100 Datasheet

113

January 26, 2016

4.6.1.

Timer Mode (MODETC = 0)

In timer mode, the counter register is incremented in each clock cycle. When the counter reaches 0xFFFF_FFFF,

the reload value is copied into the counter register and it sets both the OVERFLOW flag bit and the interrupt line.

The OVERFLOW bit (see Table 4.17) and interrupt line are set high for one clock cycle.

When reload mode is enabled (bit MODESR = 0 in the T32_CTRL register), the counter continues counting.

Otherwise the counter stops. The two other control bits, MODELE and MODEPN in the T32_CTRL register, have

no meaning in this mode.

4.6.2.

Counter Mode (MODETC = 1)

The counter register is incremented in each clock cycle when the trigger is active. When the counter has a value

of 0xFFFF_FFFF and the trigger is active, the reload value is copied into the counter register and the

OVERFLOW bit and the interrupt line are set high for one clock cycle. When the reload mode is enabled

(MODESR = 0 in the T32_CTRL register), the counter continues counting. Otherwise the counter stops.

The two control bits MODELE and MODEPN are used to configure the trigger as shown in Table 4.4.

Table 4.4

Configuration of Timer Trigger Behavior

MODELE

MODEPN

Sensitivity

Behavior

Falling Edge

Trigger is active when trigger input has a falling edge between clock cycles.

Rising Edge

Trigger is active when trigger input has a rising edge between clock cycles.

LOW

Trigger is active when trigger input is low.

HIGH

Trigger is active when trigger input is high.

4.6.3.

TIMER Module Interrupt

The timer has an interrupt line that is active-high and set high for a single clock cycle whenever the counter

overflows. The interrupt line is connected to the ARM® interrupt 4.

4.6.4.

TIMER Module Registers

The TIMER module uses the following registers:

•

T32_CTRL

TIMER control and configuration register (Table 4.17)

•

T32_TRIGSEL Trigger select register (Table 4.18)

•

T32_CNT

•

T32_REL

For detailed register address mapping and bit descriptions, refer to section 4.10.3.

4.7.

SysTick

The Cortex™-M0 core has an integrated SysTick module. For configuration information, refer to the ARM®

Cortex™-M0 Documentation Kit.

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