ZAMC4100GA2R datasheet(116/156 Pages) RENESAS

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ZAMC4100 Datasheet

116

January 26, 2016

RXOVERFLOW: This bit is set by hardware when it is not able to store a received byte into the RX buffer (RX

buffer is already full). It is cleared by a software READ access to the status register. To prevent losing any

information, the set condition has higher priority than the clear condition. This bit is not set when the byte in the

RX buffer is read in the same system clock cycle when the next received byte will be stored.

RXFULL: This bit is set by hardware when a received byte is stored into the RX buffer and cleared when the byte

is read by the software. To prevent losing any information, the set condition has higher priority than the clear

condition. This situation occurs when the byte in the RX buffer is read in the same system clock cycle when the

next received byte will be stored.

TXEMPTY: This flag is active on default. It is cleared when software writes a byte to the TX buffer and is set by

hardware when it moves this byte into the shift register. As it might be possible that both actions happen in the

same system clock cycle, the clear condition has the higher priority.

WRCOLLISION: This flag is set when the software writes a byte into the TX buffer while the TX buffer is not

empty and its contents have not been moved into the shift register in the same system clock cycle. The byte that

the software intends to write is rejected to avoid loss of data. It is cleared by a software READ access to the

status register.

4.8.7.

Syncing the Data Transfer Rate via a Software Pause

When the software is not able to read the RX byte before the next byte is received (RXOVERFLOW bit = 1 in the

Z1_SPISTAT register), the timing can be relaxed by not writing the second TX byte until the first RXFULL interrupt

in the Z1_SPISTAT register. Instead the second TX byte can be written after this interrupt. This guarantees that

no RX overflow can occur but introduces some delay between two consecutive bytes as the module waits for the

next byte transfer until data is present.

4.8.8.

Master SPI Registers

The following registers are used by the SPI MASTER module:

•

Z1_SPICFG

SPI configuration register

•

Z1_SPIDATA

READ/WRITE access to this register accesses the SPI RX data buffer and the TX data

buffer respectively

•

Z1_SPICLKCFG SPI clock configuration

•

Z1_SPISTAT

Collects SPI status flags

For detailed register address mapping and bits description, refer to section 4.10.4.

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