ZAMC4100GA2R datasheet(119/156 Pages) RENESAS

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ZAMC4100 Datasheet

119

January 26, 2016

Although the fields to be received and transmitted have the same structure as a UART, the control logic is

different as the TX and RX channel are not independent. Each transfer consists of 8 data bits enclosed by a

leading START bit and a trailing STOP bit. On reception, the receiver synchronizes on the falling edge of the RXD

line (START) and samples the incoming data stream in the middle of each data bit. Additionally it checks that the

STOP bit is high. For transmission, the module itself generates the data stream, but it also checks that it can

receive the bits sent on its RXD line.

Figure 4.9 Frame Format of Each LIN Field (PID, DATA, Checksum) and RX Sample Position

START

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

STOP

RX SAMPLING

(BAUDRATE+1)

/ F(MODULE)

4.9.4.

Description of the Receive Operation

The receive path is directly controlled by the LIN bus. Whenever a valid BREAK and SYNC field is detected by

the BREAK/SYNC field detector, the baud rate registers are updated, the receiver is enabled (RXEN bit is set to 1

in the Z1_LINCFG register; see Table 4.25) but placed into an inactive state (RXACTIVE bit is set to 0 in

Z1_LINCFG), and the RX control logic is set appropriately. Additionally, the SYNCDET interrupt flag in the

LINSTAT register (Table 4.26) is set, which must be cleared by software. If the receiver was already active on

reception of the sync strobe, the active transfer is discarded as it was receiving a new SYNC field.

After being enabled in inactive state, the bus is observed for a START condition (falling edge on the RXD line).

When a START condition is detected, the receiver is placed into the active state (RXACTIVE bit is set to 1 in the

Z1_LINCFG). The data is sampled into the shift register in the middle of each data bit. When the complete byte

has been shifted in, the receiver is placed back into its inactive state in the middle of the STOP bit. When the

STOP bit is high (as it should be), the received byte is placed into the RX buffer if this buffer is empty and then the

buffer is marked as full (RXFULL bit is set to 1 in LINSTAT). Otherwise the actual received byte is rejected and

the RX overflow flag is set (RXOVERFLOW bit is set to 1 in LINSTAT). If the STOP bit is low (wrong baud rate

detection or another BREAK and SYNC field is send by the master), no data is placed into the RX buffer. Instead

the receiver is disabled (RXEN bit is set to 0 in Z1_LINCFG) and a new BREAK/SYNC field is needed to restart

the receiver.

After the first byte (PID) was received, the receiver remains enabled but inactive as a DATA byte can be sent via

the bus by the LIN master or another slave. In parallel, triggered by the RXFULL flag bit in the LINSTAT register,

the software must read the received byte (PID) and must determine how to proceed. If the PID signals that the

SW-LIN will receive data bytes, no more actions need to be taken as the receiver remains enabled. The software

only has to wait for the next RXFULL interrupt bit for the successful reception of the first data byte. If the PID

indicates that this module is not part of the following transfer or if the last byte (checksum) has been received,

software should stop the receiver. This is done by writing 1 to the STOPRX bit in Z1_LINCFG. This register is a

strobe register (cleared after one clock cycle) and is used to clear both the RXEN bit and RXACTIVE flag in

Z1_LINCFG, as well as to place the RX control logic into a safe state.

ZAMC4100GA2R Datasheet(PDF) 119 Page - Renesas Technology Corp

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