ZAMC4100GA2R datasheet(123/156 Pages) RENESAS

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ZAMC4100 Datasheet

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January 26, 2016

4.10. MCU Registers Description

4.10.1.

System Registers

The SMU registers are mapped into the system address space between 0x4000_0000 and 0x4000_03FF.

Unused addresses must not be accessed.

Table 4.5

SYS_CLKCFG

ADD: 0x4000_0000

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

1:0

CLKDIV

R / W

Clock divider value:

0: Incoming clock is divided by 1

1: Incoming clock is divided by 2

2: Incoming clock is divided by 4

3: Incoming clock is divided by 8

6 : 2

---

Unused; always read as 0.

---

R/W

Reserved.*

31 : 8

---

Unused; always read as 0.

Table 4.6

SYS_MEMPORTCFG

ADD: 0x4000_0004

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

7 : 0

PPNOD

R / W

Output configuration bits.

It can be individually selected for each GPIO whether it

functions as an open-drain (set to 0) or as a push-pull

(set to 1).

15 : 8

N/A

Reserved.

17 : 16

N/A

Reserved, do not write to these bits.

20 : 18

N/A

Reserved, do not write to these bits.

23 : 21

N/A

Reserved, do not write to these bits.

29 : 24

---

Unused; always read as 0.

LINTEST

R / W

Configuration bit for LIN test. When set, RXD and TXD

lines are directly connected to the GPIO.

MEMSWAP

R / W

Memory swap bit. It can be selected whether the FLASH

MAIN area (set to 0) or the RAM (set to 1) will be

mirrored to system address 0x0.

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