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ZAMC4100GA2R Datasheet(PDF) 124 Page - Renesas Technology Corp |
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ZAMC4100GA2R Datasheet(HTML) 124 Page - Renesas Technology Corp |
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124 / 156 page ![]() ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 124 January 26, 2016 Table 4.7 Register [0x4000_0008] SYS_MEMINFO SYS_MEMINFO ADD: 0x4000_0008 Bit Name Ext. Access Int. Access Reset Value Description 7 : 0 PROGSTART R R / W 0xFF This register represents the first page where the program section inside the FLASH starts. This value is read from FLASH during the power-up phase and is updated by some flash commands. Note: To determine the correct FLASH address offset, seven "0" must be appended. 15 : 8 LOGSTART R R / W 0xFF This register represents the first page where the log section inside the FLASH starts. This value is read from the FLASH during the power-up phase and is updated by some FLASH commands. Note: To determine the correct FLASH address offset, seven "0" must be appended. 26 : 16 RAMSPLIT R R / W 0x7FF This register represents the first RAM word that is accessible by JTAG although the memory is locked. This value is read from FLASH during the power-up phase and is updated by some FLASH commands. Note: To determine the correct RAM address offset, two "0" must be appended. 27 --- R --- 0 Unused; always read as 0. 31 : 28 PROTINFO R R / W 0xF This register represents the memory protection scheme. This value is read from FLASH during the power-up phase and is updated by some FLASH commands. [0]: key-based lock [1]: permanent lock [3:2]: number of failed unlock attempts Table 4.8 Register [0x4000_000C] SYS_RSTSTAT SYS_RSTSTAT ADD: 0x4000_000C Bit NAME Ext. Access Int. Access Reset Value Description 0 EXTRST RC --- 1 This bit reflects if an external reset has occurred. It is cleared when the register is read. 1 SYSRSTREQ RC W 0 This bit reflects if a reset forced by a system reset request has occurred. It is cleared when the register is read. 2 LOCKUPRST RC W 0 This bit reflects if a reset was forced by a detected lockup when this reset was enabled. It is cleared when the register is read. 3 JTAGRST RC W 0 This bit reflects if a reset that was forced by a JTAG reset request has occurred. It is cleared when the register is read. 6 : 4 --- R --- 0 Unused; always read as 0. |
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