ZAMC4100GA2R datasheet(128/156 Pages) RENESAS

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ZAMC4100 Datasheet

128

January 26, 2016

4.10.3.

32 Bit Timer Registers

The 32-bit timer registers are mapped into the system address space between 0x4000_1000 and 0x4000_13FF.

Unused addresses must not be accessed.

Table 4.17 Register [0x4000_1000] T32_CTRL

T32_CTRL

ADD:0x4000_1000

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

R / W

Enable bit for timer. This bit is cleared by hardware if an over-

flow occurs and the module is operating in single shot mode.

MODETC

R / W

Select between timer and counter mode:

0: timer mode

1: counter mode

MODESR

R / W

Select between reload and single shot mode:

0: reload mode; at overflow, reload value is copied into

counter register and counter continues

1: single shot mode; at overflow, reload value is copied into

counter register and counter stops

MODELE

R / W

Select between level or edge sensitive trigger;

counter mode only:

0: trigger is used as level sensitive

1: trigger is used as edge sensitive

MODEPN

R / W

Selects between rising or falling edge active trigger

(MODELE = 1) or high or low level (MODELE = 0);

counter mode only

0: Trigger on falling edge/low level

1: Trigger on rising edge/high level

OVERFLOW

R / W

Overflow flag (strobe); set for a single cycle when counter

overflows. This bit also drives the interrupt line.

31 : 6

---

Unused; always read as 0.

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