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ZAMC4100GA2R Datasheet(PDF) 130 Page - Renesas Technology Corp

Part # ZAMC4100GA2R
Description  Actuator and Motor Controller
PDF  156 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ZAMC4100GA2R Datasheet(HTML) 130 Page - Renesas Technology Corp

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ZAMC4100 Datasheet
© 2016 Integrated Device Technology, Inc.
130
January 26, 2016
4.10.4.
SPI Registers
The registers of the SPI module are mapped into the system address space between 0x4000_1820 and
0x4000_1BFF. Unused addresses must not be accessed.
Table 4.21 Register [0x4000_1820] Z1_SPICFG
Z1_SPICFG
ADD:0x4000_1820
Bit
Name
Ext.
Access
Int.
Access
Reset
Value
Description
0
RXOVERFLOW
R / W
R
0
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
1
RXFULL
R / W
R
0
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
2
TXEMPTY
R / W
R
0
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
3
WRCOLL
R / W
R
0
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
4
---
R
---
0
Unused; always read as 0.
5
SAMPLEPOS
R / W
R
0
This bit selects whether data on MISO will be sampled at the
sampling edge (set to 0) or at shift edge (set to 1).
Note: Change this bit only when the module is disabled
(SPIEN = 0) or when no transfer is in progress.
6
SSN
R / W
R / W
1
This bit directly controls the SSN line.
7
SPIEN
R / W
R / W
0
Enable for SPI module.
31 : 8
---
R
---
0
Unused; always read as 0.
Table 4.22 Register [0x4000_1824] Z1_SPIDATA
Z1_SPIDATA
ADD:0x4000_1824
Bit
Name
Ext.
Access
Int.
Access
Reset
Value
Description
7 : 0
SPIDATA
R / W
R / W
0
When writing a byte to this register, the value is stored in the
TxBuffer. Additionally a WRITE access to this register clears
the TXEMPTY flag in the Z1_SPISTAT register (Table 4.24).
When reading this register, the contents of the RxBuffer is
returned. Additionally a READ access to this register clears
the RXFULL flag in Z1_SPISTAT.
Note: When writing to this register when TxBuffer is full, the
TxBuffer keeps its contents and the written byte is rejected.
This is signaled by the WRCOLL flag in Z1_SPISTAT.
31 : 8
---
R
---
0
Unused; always read as 0.



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