ZAMC4100GA2R datasheet(133/156 Pages) RENESAS

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ZAMC4100 Datasheet

133

January 26, 2016

Z1_LINCFG

ADD:0x4000_1800

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

31 : 7

---

Unused; always read as 0.

Table 4.26 Register [0x4000_1804] Z1_LINSTAT

Z1_LINSTAT

ADD:0x4000_1804

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

SYNCDET

R / W

This bit is set by hardware when a BREAK/SYNC field has

been detected by the break-/sync-field detector. It is cleared

when software reads this register.

RXFULL

R / W

This bit is set by hardware when a received byte is placed into

the RX buffer. It is cleared when the software reads the data

out of the RX buffer (read from LINDATA;Table 4.27).

TXEMPTY

R / W

This bit is set when a byte to be transmitted is read out of the

TX buffer to be shifted out on the LIN bus. It is cleared when

the software puts a new byte into the TX buffer (write to

LINDATA).

CONFLICT

R / W

This bit is set by hardware when it has detected a bus conflict

during an active transmission. This can only occur when

sending a 1 but receiving a 0. It is cleared when software

reads this register.

RXOVERFLOW

R / W

This bit is set by hardware if the receiver attempts to place a

received byte into the RX buffer while this buffer is already

full. The new received byte is rejected and lost. This bit is

cleared when software reads this register.

WRCOLL

R / W

This bit is set by hardware if software tries to write a byte into

the TX buffer while this buffer is already full. The new written

byte is rejected. This bit is cleared when the software reads

this register.

TXOFF

R / W

This bit is set by hardware if it is transmitting a 0 but receives

a 1. As 0 is the dominant level on the bus; this can only occur

due to hardware error or if the bus protection circuit has

disabled the output driver in the LIN PHY. This bit is cleared

when software reads this register.

INACTIVE

R / W

This bit is set when the timeout counter for inactivity has

expired. This bit is cleared when software reads this register.

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