 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ZAMC4100GA2R Datasheet(PDF) 137 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
ZAMC4100GA2R Datasheet(HTML) 137 Page - Renesas Technology Corp |
|
|
137 / 156 page  ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 137 January 26, 2016 Table 4.34 Register [0x4000_0808] FC_CMD_SIZE FC_CMD_SIZE ADD:0x4000_0808 Bit Name Ext. Access Int. Access Reset Value Description 3 : 0 COMMAND R / W R 0 Command to be executed by flash controller Valid commands: 0HEX: ERASE_MAIN_CMD 2HEX: ERASE_BOOT_PROG_CMD 3HEX: ERASE_PROG_CMD 4HEX: ERASE_MAINPAGE_CMD 6HEX: ERASE_KEY_CMD 8HEX: UNLOCK_CMD 9HEX: GETENV_CMD AHEX: WRITE_CMD CHEX: SET_KEY_CMD DHEX: SET_BOUNDARY_CMD EHEX: LOCK_PERM_CMD FHEX: LOCK_KEY_CMD 7:4 --- R --- 0 Unused; always read as 0. 12:8 WRSIZE R / W R 0 Number of words to be written to FLASH; 0 is interpreted as 32. Note: Writing is always performed within a row. 1 row contains 32 words. While the RAM address is always incremented, the FLASH address wraps at the row boundary to the beginning of the row. It is in the responsibility of the user to ensure this. 31 : 13 --- R --- 0 Unused; always read as 0. Table 4.35 Register [0x4000_0810] FC_IRQ_EN FC_IRQ_EN ADD:0x4000_0810 Bit Name Ext. Access Int. Access Reset Value Description 0 ENIRQ0 R / W R 0 When set to 1, the status signal CMDRDY in the FC_STAT_CORE register is allowed to drive the interrupt line. See Table 4.36 for the related status signals for bits [3:0] this register. 1 ENIRQ1 R / W R 0 When set to 1, the status signal INVALIDCMD is allowed to drive the interrupt line. 2 ENIRQ2 R / W R 0 When set to 1, the status signal INVALIDAREA is allowed to drive the interrupt line. 3 ENIRQ3 R / W R 0 When set to 1, the status signal UNLOCKFAIL is allowed to drive the interrupt line. 4 ENIRQ4 R / W R 0 When set to 1, the status signal DATAALL1 in the FC_STAT_DATA register is allowed to drive the interrupt line. See Table 4.38 for the related status signals for bits [6:4] this register. 5 ENIRQ5 R / W R 0 When set to 1, the status signal DATA1ERR is allowed to |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
