ZAMC4100GA2R datasheet(138/156 Pages) RENESAS

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ZAMC4100 Datasheet

138

January 26, 2016

FC_IRQ_EN

ADD:0x4000_0810

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

drive the interrupt line.

ENIRQ6

R / W

When set to 1, the status signal DATA2ERR is allowed to

drive the interrupt line.

ENIRQ7

R / W

When set to 1, the status signal PROG1ERR in the

FC_STAT_PROG register (Table 4.37) is allowed to drive the

interrupt line.

31 : 8

---

Unused; always read as 0.

Table 4.36 Register [0x4000_0814] FC_STAT_CORE

FC_STAT_CORE

ADD:0x4000_0814

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

CMDRDY

R / W

This bit is set when a command execution has finished; it is

cleared when this register is read.

INVALIDCMD

R / W

This bit is set when an invalid command was executed; it is

cleared when this register is read.

INVALIDAREA

R / W

This bit is set when a command is executed targeting a

protected area; e.g., performing ERASE_MAINPAGE_CMD

to program space when flash is locked; it is cleared when this

UNLOCKFAIL

R / W

This bit is set when the UNLOCK_CMD fails; it is cleared

when this register is read.

COREACTIVE

R / W

This bit reflects the status of the core state machine; when

set core is active.

ALLOWKEY

R / W

When this bit is set but FLASH is locked, the

ERASE_KEY_CMD is allowed to be performed.

ALLOWBOOT

R / W

When this bit is set but FLASH is locked, the WRITE_CMD is

allowed to be performed on the boot space.

ALLOWPROG

R / W

When set but FLASH is locked, the WRITE_CMD is allowed

to be performed on the program space.

CLRALLOW

W1C

Writing 1 to this bit clears ALLOWKEY, ALLOWBOOT, and

ALLOWPROG flags.

31 : 9

---

Unused; always read as 0.

For related FLASH controller command codes, see Table 4.34.

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