ZAMC4100GA2R datasheet(136/156 Pages) RENESAS

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ZAMC4100 Datasheet

136

January 26, 2016

4.10.6.

FLASH Memory Registers

The registers of the FLASH controller are mapped into the system address space between 0x4000_0800 and

0x4000_0BFF. Unused addresses must not be accessed. Read accesses to registers are always performed even

if a command is executed or a direct WRITE is active. Write accesses to the registers are postponed until the

active command/direct-write access has finished.

Table 4.31 Register [0x4000_0800] FC_RAM_ADDR

FC_RAM_ADDR

ADD:0x4000_0800

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

10 : 0

ADDRRAM

R / W

RAM word address where data to be written into flash is

located (first address); hardware increments this address

when more than one word has to be written.

Note: The last two address digits of the RAM are not included

as they are always 0. For programming, the RAM address

needs to be shifted right by two bits.

31 : 11

---

Unused; always read as 0.

Table 4.32 Register [0x4000_0804] FC_FLASH_ADDR

FC_FLASH_ADDR

ADD:0x4000_0804

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

14 : 0

FLASHADD

R / W

FLASH word address (first address) where data is to be

written; also used as the pointer to a page to be erased.

Note: the last two address digits of the FLASH are not

included as they are always 0. For programming, the FLASH

address needs to be shifted right by nine bits.

31 : 15

---

Unused; always read as 0.

Table 4.33

FC_EXE_CMD

ADD:0x4000_080C

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

EXECMD

R / W

Writing 1 to this bit starts the execution of the configured

command; always read as 0.

31 : 1

---

Unused; always read as 0.

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