ZAMC4100GA2R datasheet(131/156 Pages) RENESAS

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ZAMC4100 Datasheet

131

January 26, 2016

Table 4.23 Register [0x4000_1828] Z1_SPICLKCFG

Z1_ SPICLKCFG

ADD:0x4000_1828

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

CPOL

R / W

Clock polarity; the content of this bit directly affects the idle

state of the clock.

Note: Change this bit only when the module is disabled

(SPIEN=0 in register Z1_SPICFG; see Table 4.21).

CPHA

R / W

Clock phase; data is centered on the first (set to 0) or to the

second (set to 1) clock edge.

Note: Change this bit only when the module is disabled

(SPIEN=0).

7 : 2

CDIV

R / W

Clock divider value; SPI clock period is 2∗(CDIV+1) times the

system clock.

Note: Change this bit only when the module is disabled

(SPIEN=0) or when no transfer is in progress.

31 : 8

---

Unused; always read as 0.

Table 4.24 Register [0x4000_182C] Z1_SPISTAT

Z1_ SPISTAT

ADD:0x4000_182C

Bit

Name

Ext.

Access

Int.

Access

Reset

Value

Description

RXOF

This bit signals that an RX overflow has occurred.

Note: This bit is cleared when the status is read.

Note: The received byte causing the overflow is rejected; the

previous received byte is kept in the RX buffer.

RXFULL

R / W

This bit reflects the status of the RX buffer. It is set when a

new byte is transferred into the RX buffer.

Note: This bit is cleared when SPIDATA is read (Table 4.22).

TXEMPTY

R / W

This bit reflects the status of the TX buffer. It is set when a

byte is transferred from the TX buffer into the shift register.

Note: This bit is cleared when SPIDATA is written.

WRCOLL

This bit is set when SPIDATA is written while TX buffer is

already full.

Note: This bit is cleared when the status is read.

BUSY

R / W

This bit reflects the status of the SPI module.

6 : 5

---

Unused; always read as 0.

CLRTXBUF

W1C

Writing a 1 to this bit clears the TX buffer.

Note: Write only when SPI is disabled; always read as 0.

31 : 8

---

Unused; always read as 0.

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