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TMPR4955AF Datasheet(PDF) 57 Page - Toshiba Semiconductor |
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TMPR4955AF Datasheet(HTML) 57 Page - Toshiba Semiconductor |
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57 / 168 page  Chapter 4 Clock Interface 4-1 Chapter 4. Clock Interface This chapter describes the clock signals (“clocks”) used in the TX4955A processor. The subject matter includes basic system clocks, system timing parameters, operating the TX4955A processor in reduced power (RP) mode, connecting clocks to a phase-locked system, and connecting clocks to a system without phase locking. 4.1 Signal Terminology The following terminology is used in this chapter (and book) when describing signals: • Rising edge indicates a low-to-high transition. • Falling edge indicates a high-to-low transition. • Clock-to-Q delay is the amount of time it takes for a signal to move from the input of a device ( clock) to the output of the device (Q). Figure 4.1.1 and Figure 4.1.2 illustrate these terms. Figure 4.1.1 Signal Transitions Figure 4.1.2 Clock-to-Q Delay single clock cycle high-to-low transition 12 3 4 low-to-high transition Clock-to-Q delay Q data in data out clock in data in data out clock-to-Q clock in |
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