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TMPR4955AF Datasheet(PDF) 67 Page - Toshiba Semiconductor |
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TMPR4955AF Datasheet(HTML) 67 Page - Toshiba Semiconductor |
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67 / 168 page  Chapter 5 Cache Organization 5-7 5.4 The primary cache accessing Figure 5.4.1 shows the virtual address (VA) index to the primary cache. Each instruction and data cache size is 32 KB. The virtual address bits be used to index into the primary cache decided by the cache size. Tags Tag line Data Data line VA (12..5) Stage WTag VA (12..5) 64 Figure 5.4.1 Primary Cache Data and Tag Organization 5.5 Cache States The section describes about the state of a cache line. The cache line in the TX4955A are in one of states described in Table 5.5.1. The I-Cache line is in one of the following states: • invalid • valid The D-Cache line is in one of the following states: • invalid • valid Table 5.5.1 Cache States Cache line State Description Invalid A cache line that does not contain valid information must be marked invalid, and cannot be used. A cache line in any other state than invalid is assumed to contain valid information. Valid A cache line contains valid information. The cache line may or not be consistent with memory and is owned by the processor (see Cache Line Ownership in this chapter). |
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