TMPR4955AF datasheet(66/168 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-6

5.3.2

Operation during lock

After the lock bit is set for a line, the line can be replaced only when it’s line state is

invalid. The locked valid line can never be replaced. FIFO bit should point only to the set

of locked invalid line or unlocked line.

A write access to a locked valid line takes place only to the cache not to the memory at

Write Back mode. Both of the cache and the memory are replaced at Write Through mode.

5.3.3

Example of Data cache locking

During the load operation to the locked line of the cache, any interrupt should be

disabled in order to avoid to lock the wrong data.

To lock data cache lines, the following sequence of codes could be used.

.......................

/* Disable the interrupt */

mtc0 t0, TagLo

/* Load data into TagLo reg */

cache 2 (D), offset (base) /* Invalidate and lock line in desired set using

Index_Store_Tag cache instruction */

cache 7 (D), offset (base) /* Fill the cache line from desired memory location */

.......................

/* Enable the interrupt */

5.3.4

Example of Instruction cache locking

To lock instruction cache lines, the following sequence of codes could be used:

.......................

/* Disable the interrupt */

mtc0 t0, TagLo

/* Load data into TagLo reg */

cache 2 (I), offset (base) /* Invalidate and lock line in desired set using

Index_Store_Tag cache instruction */

cache 5 (I), offset (base) /* Fill the cache line from desired memory location */

.......................

/* Enable the interrupt */

TMPR4955AF Datasheet(PDF) 66 Page - Toshiba Semiconductor