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TMPR4955AF Datasheet(PDF) 68 Page - Toshiba Semiconductor |
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TMPR4955AF Datasheet(HTML) 68 Page - Toshiba Semiconductor |
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68 / 168 page  Chapter 5 Cache Organization 5-8 5.6 Cache Line Ownership The TX4955A becomes the owner of a cache line after it writes to that cache line (that is, by entering the dirty exclusive), and is responsible for providing the contents of that line on a read request. There can only be one owner for each cache line. 5.7 Cache Multi-Hit Operation The TX4955A is not guaranteed the operation for the multi-hit of primary cache. Thus, in case of locking the specified program/data in the primary cache, the program/data must be used after locked in the cache by Fill instruction. Such as the previous description the cache multi hit does not guarantee in the TX4955A, however, if it occurs, the TX4955A will do the operation as follows. • Load: read from the higher way of priority (way0 > way1 > way2 > way3). • Store: write to all way that are multi-hits. 5.8 FIFO Replacement Algorithm The instruction and data caches in the TX4955A use the FIFO replacement algorithm. • Usually, cache elements are replaced in this order: Way0, Way1, Way2, Way3. • The FIFO[1:0] replacement bits do not point to a locked, valid cache line. • Data is first written to a cache line marked invalid, if any. • The FIFO replacement bits change every time memory data is written to the cache or a CACHE instruction is executed. Figure 5.8.1 shows several examples of how the FIFO replacement bits change. A) Way0 Invalid Way1 Invalid Way2 Invalid Way3 Invalid B) C) D) Way0 Invalid Way1 Invalid Lock Way2 Invalid Way3 Invalid Way0 Invalid Way1 Invalid Way2 valid Way3 Invalid Way0 Invalid Way1 valid Lock Way2 Invalid Way3 valid E) F) Way0 Invalid Way1 valid Lock Way2 valid Lock Way3 valid Lock Way0 valid Way1 valid Way2 valid Lock Way3 valid Figure 5.8.1 Examples of Cache State Transitions by the FIFO Replacement Algorithm |
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