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TMS320DM647 Datasheet(PDF) 38 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 166 page  www.ti.com 3 Device Configuration 3.1 System Module Registers 3.2 Bootmode Registers 3.2.1 Boot Configuration (BOOTCFG) Register TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. System Module registers required for device configuration are described in the following sections. Table 3-1. System Module Register Memory Map HEX ADDRESS RANGE REGISTER NAME DESCRIPTION 0x0204 9000 PINMUX Pin multiplexing control 0 0x0204 9004 Reserved 0x0204 9008 DSPBOOTADDR Boot Address of DSP, decoded by bootloader software for host boots 0x0204 900C BOOTCMPLT Boot Complete 0x0204 9010 Reserved 0x0204 9014 BOOTCFG Device boot configuration 0x0204 9018 JTAGID Device ID number. See Section 6.23 for details. 0x0204 901C PRI_ALLOC Bus master priority control See Section 4 for details 0x0204 9020 -0x0204 9053 Reserved Reserved 0x0204 9054 KEY_REG Key Register to protect against accidental writes. 0x0204 9060 - 0x0204 90A7 Reserved Reserved 0x0204 90A8 CFGPLL CFGPLL inputs for SerDes 0x0204 90AC CFGRX0 Configure SGMII0 RX 0x0204 90B0 CFGTX0 Configure SGMII0 TX 0x0204 90B4 CFGRX1 Configure SGMII1 RX 0x0204 90B8 CFGTX1 Configure SGMII1 TX 0x0204 90BC Reserved Reserved 0x0204 90C0 Reserved Reserved 0x0204 90C4 MAC_ADDR_R0 MAC Address Read Only Register 0 0x0204 90C8 MAC_ADDR_R1 MAC Address Read Only Register 1 0x0204 90CC MAC_ADDR_RW0 MAC Address Read/Write Register 0 0x0204 90D0 MAC_ADDR_RW0 MAC Address Read/Write Register 1 0x0204 90D4 ESS_LOCK Ethernet Sub System Lock Register The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status levels of various pins required for proper boot are stored within these registers. Configuration pins latched at reset are presented in the BOOTCFG register accessible through the system module. This is a read-only register. The bits show the true latched value of the corresponding input at RESET or POR deassertion. This is desirable since the most important use of this MMR is for the user to debug/view the actual value driven on the pins during device reset. Device Configuration 38 Submit Documentation Feedback |
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