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6.3.6

Preserving Boundary-Scan Functionality on DDR2 Memory Pins

6.4 PLL1 and PLL1 Controller

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

Similarly, when the DDR2 Memory Controller is not used, the VREFSSTL, RSV19, and RSV20 pins can be

connected directly to ground (VSS) to save power. However, this will prevent boundary-scan from

functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2

Memory Controller pins, VREFSSTL, RSV11, and RSV12 should be connected as follows:

• V

REFSSTL - connect to a voltage of DVDD18/2. The DVDD18/2 voltage can be generated directly from

the DVDD18 supply using two 1-kΩ resistors to form a resistor divider circuit.

• RSV19 - connect this pin to ground (V

SS) via a 200-Ω resistor.

• RSV20 - connect this pin to the 1.8-V I/O supply (D

VDD18) via a 200-Ω resistor

The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as

well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the

external memory interface (EMIFA).

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Peripheral Information and Electrical Specifications

TMS320DM647 Datasheet(PDF) 63 Page - Texas Instruments