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TMS320DM647 Datasheet(PDF) 88 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 166 page  www.ti.com CLKIN1 PCLK RESET RESETST AT SYSREFCLK(PLL1C) ZGroup POR SYSCLK3 SYSCLK4 SYSCLK5 AECLKOUT (Internal) BootandDevice ConfigurationPins LowGroup HighGroup CLKIN2 InternalResetPLL2C SYSREFCLK(PLL2C) SYSCLK1(PLL2C) SYSCLK2 5 9 7 8 Undefined Undefined Low High-Z Undefined High PLL2Unlocked PLL2Locked (A) PLL2Unlocked ClockV alid Undefined Undefined Undefined ClockV alid(B) PowerSuppliesRamping PowerSuppliesStable TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 A. SYSREFCLK of the PLL2 controller runs at CLKIN2 ×10. B. SYSCLK1 of PLL2 controller runs at SYSREFCLK/2 (default). C. Power supplies, CLKIN1, CLKIN2 (if used), and PCLK (if used) must be stable before the start of tw(POR). Figure 6-10. Power-Up Timing Peripheral Information and Electrical Specifications 88 Submit Documentation Feedback |
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