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TMS320DM647 Datasheet(PDF) 70 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 166 page  www.ti.com 6.6 Enhanced Direct Memory Access (EDMA3) Controller 6.6.1 EDMA3 Channel Synchronization Events TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 The EDMA controller handles all data transfers between memories and the device slave peripherals on the DM648 device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. These are summarized as follows: • Transfer to/from on-chip memories – DSP L1D memory – DSP L2 memory • Transfer to/from external storage – DDR2 SDRAM – Synchronous/Asynchronous EMIF (EMIFA) • Transfer to/from peripherals/hosts – VLYNQ – HPI – McASP – UART – Video Port 0/1/2/3/4 – Timer 0/1/2/3 – SPI – I2C The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 6-13 lists the source of EDMA synchronization events associated with each of the programmable EDMA channels. For the DM648 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide (literature number SPRUEL2). Table 6-13. EDMA Channel Synchronization Events TPCC DEFAULT BINARY DEFAULT EVENT TPCC DEFAULT BINARY DEFAULT EVENT CHANN EVENT# CHANNEL EVENT # EL 0 0 000 0000 HPI/PCI : DSPINT 32 32 010 0000 VP2EVTYA 1 1 000 0001 TIMER0 : TINT0L 33 33 010 0001 VP2EVTUA 2 2 000 0010 TIMER0 : TINT0H 34 34 010 0010 VP2EVTVA 3 3 000 0011 TIMER2 : TINT2L 35 35 010 0011 VP2EVTYB 4 4 000 0100 TIMER2 : TINT2H 36 36 010 0100 VP2EVTUB 5 5 000 0101 TIMER3 : TINT3L 37 37 010 0101 VP2EVTVB 6 6 000 0110 TIMER3 : TINT3H 38 38 010 0110 VP3EVTYA 7 7 000 0111 IMCOP: IMXINT 39 39 010 0111 VP3EVTUA 8 8 000 1000 IMCOP: VLCDINT 40 40 010 1000 VP3EVTVA 9 9 000 1001 IMCOP: DSQINT 41 41 010 1001 VP3EVTYB 10 10 000 1010 McASP: AXEVTE 42 42 010 1010 VP3EVTUB 11 11 000 1011 McASP: AXEVTO 43 43 010 1011 VP3EVTVB 12 12 000 1100 McASP: AXEVT 44 44 010 1100 ICREVT 13 13 000 1101 McASP: AREVTE 45 45 010 1101 ICXEVT 14 14 000 1110 McASP: AREVTO 46 46 010 1110 SPI: SPIXEVT Peripheral Information and Electrical Specifications 70 Submit Documentation Feedback |
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