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TMS320DM647 Datasheet(PDF) 90 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 90 Page - Texas Instruments |
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90 / 166 page  www.ti.com 6.8 Interrupts TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable. Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts and the generation of AEG events. Table 6-26 summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP interrupt control, see TMS320DM647/DM648 DMP DSP Subsystem Reference Guide (literature number SPRUEU6). Table 6-25. DM647/DM648 DSP Interrupts DSP EVENT INTERRUPT SOURCE INTERRUPT NUMBER 0 EVT0 Output of event combiner 0, for events 1 – 31 1 EVT1 Output of event combiner 1, for events 32 – 63 2 EVT2 Output of event combiner 2, for events 64 – 95 3 EVT33 Output of event combiner 3, for events 96 – 127 4-8 Reserved 9 EMU_DTDMA ECM interrupt for: • Host scan access • DTDMA transfer complete • AET interrupt 10 Reserved Reserved 11 EMU_RTDXRX RTDX receive complete 12 EMU_RTDXTX RTDX transmit complete 13 IDMA0 EMC C64x+ EMC 0 14 IDMA1 EMC C64x+ EMC 1 15 HINT Host interrupt 16 I2CINT I2C interrupt 17 Reserved Reserved 18 AEASYNCERR EMIFA Error Interrupt 19 TINT2L Timer interrupt low 20 TINT2H Timer interrupt high 21 TINT3L Timer interrupt low 22 TINT3H Timer interrupt high 23 PSCINT PSC-ALLINT 24 TPCC_GINT EDMA3 channel global completion interrupt 25 SPIINT0 SPI Interrupt 26 SPIINT1 SPI Interrupt 27 DSQINT VICP – Sqr (DSP int) 28 IMXINT VICP – IMX 29 VLCDINT VICP - VLCD 30 -31 Reserved 32 RX_PULSE Ethernet Subsystem RX pulse interrupt 33 RX_THRESH_PULSE Ethernet Subsystem RX threshold interrupt 34 TX_PULSE Ethernet Subsystem TX pulse interrupt 35 MISC_PULSE Ethernet Subsystem MISC pulse interrupt 36 UART_INT UART Interrupt 37 VP0_INT VP0 Interrupt 38 VP1_INT VP1 Interrupt 39 VP2_INT VP2 Interrupt Peripheral Information and Electrical Specifications 90 Submit Documentation Feedback |
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