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TMS320DM647 Datasheet(PDF) 39 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 166 page  www.ti.com 3.2.2 DSPBOOTADDR Register Description TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 Figure 3-1. BOOTCFG Register 31 24 Reserved R-0 23 22 21 20 19 18 17 16 AECLKINSEL PC166 HPIWIDTH Reserved FASTBOOT Reserved DUHPIEN EMIFAWIDTH R-L R-1 R-L R-1 R-L R-L 15 8 Reserved 7 4 3 0 Reserved BOOTMODE R-0 R-L LEGEND: R/W = Read/Write; R = Read only; L = latched; -n = value after reset Table 3-2. BOOTCFG Register Field Descriptions Bit Field Value Description 31:24 Reserved Reserved 23 AECLKINSEL Controls the clock input for EMIFA. Latched from AECLKINSEL at RESET or POR deassertion 1 EMIFA clocked from internal SYSCLK 0 EMIFA clocked from outside from AECLKIN 22 PCI66 Controls PCI speed. PCI. Latched from PCI66 at RESET or POR deassertion 0 33 MHz PCI 1 66 MHz 21 HPIWIDTH Controls HPI bus width. Latched from HPIWIDTH at RESET or POR deassertion 0 16 bit 1 32 bit 20 Reserved 1 Reserved 19 FASTBOOT Fast Boot. Latched from FASTBOOT at RESET or POR deassertion 0 No Fast Boot 1 Fast Boot 18 Reserved Reserved 17 DUHPIEN PCI Enable Default. Latched from UHPIEN at RESET or POR deassertion 0 UHPI disabled 1 UHPI enabled 16 EMIFAWIDTH EMIFA CS2 Bus Width Default. Latched from EMIFAWIDTH at RESET or POR deassertion 0 8-bit 1 16-bit 15:4 Reserved Reserved 3:0 BOOTMODE Boot Mode. Latched from BOOTMOD at RESET or POR deassertion The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register format is shown in Figure 3-2 and bit field descriptions are shown in Table 3-3. DSPBOOTADDR is readable and writable by software after reset. DSPBOOTADDR Decode: This decode logic determines the default of the DSPBOOTADDR Register. It can default to either the base address of L2 ROM (0x00800000) or the base address of EMIFA CS2 (0xA0000000) Submit Documentation Feedback Device Configuration 39 |
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