TMS320DM647 datasheet(45/166 Pages) TI

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3.2.7

ESS_LOCK

3.2.8

MAC Address Registers

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

Table 3-7. PCI/UHPI/GPIO Block: PCI MUXed With UHPI and GPIO[0:7]

MUXED(1)

PCI

UHPI/GPIO[0:7]

UHPIEN (pin)

UHPI/GPIO[0:7]

PCI

(1)

The complete list of pin:AA22, AB22, AC21, AA23, AC22, AB21, AA21, Y21, AB20, AA20, Y20, Y19, AB18, AA19, AC18, AA18, Y16,

AB15, AA15, Y15, W15, V15, AC14, AB14, W14, V14, AC13, AB13, AA13, Y13 , W13, V13, W19, Y18, Y17, W17, W18, AC20, AC17,

W16, Y14, AC15, AA16, AB17, U13, U12, V12, AA12, AA17, AA14.

For information on the Ethernet Subsystem registers, see the TMS320DM647/DM648 DMP DSP

Subsystem Reference Guide (literature number SPRUEU6).

Figure 3-7. SerDes Macro Configuration (SERDES_CFG_CNTL) Register

Reserved

MPY

ENPLL

R-0

R/W-0

R-0

R/W-1001

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The ESS_LOCK register protects the Ethernet Subsystem MMR space (0x02D0 0000 - 0x02D0 4FFF)

and the Ethernet Subsystem's LPSC (LPSC34) MDCTL register (0x0204 6088). The default value of

ESS_LOCK is 0x0000 0000 and read/write is allowed to Ethernet Subsystem MMR space and MDCTL

[34]. To lock the write access to both Ethernet Subsystem MMR space and MDCTL [34], software must

write a value of 0x AAAA AAAA to the ESS_LOCK register. To make sure that the desired lock has been

achieved, the software must read the ESS_LOCK register till it gets a value of 0x1. The software must

make sure that there are no pending accesses to either the Ethernet Subsystem MMR space or MDCTL

[34]. Read access to both Ethernet Subsystem MMR space and MDCTL [34] should be unaffected while

write accesses are locked. To unlock the write access to Ethernet Subsystem MMR space and MDCTL

[34], the software must write a value of 0xCCCC CCCC to ESS_LOCK. To make sure that the desired

write lock has been removed, the software must read ESS_LOCK till it gets a value of 0x0.

Figure 3-8. ESS_LOCK Register

ESS_LOCK

R/W-0x00000000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

• MAC_ADDR_R0

• MAC_ADDR_R1

• MAC_ADDR_RW0

• MAC_ADDR_RW1

In DM647/DM648, two sets of registers provide default MAC addresses for the device. One set -

MAC_ADDR_R0 and MAC_ADDR_R1 - is read only and the other set - MAC_ADDR_RW0 and

MAC_ADDR_RW1 - includes read and write registers.

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