TMS320DM647 datasheet(61/166 Pages) TI

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6.3.5

DM647/DM648 Power and Clock Domains

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

Table 6-3. PSC Register Memory Map (continued)

HEX ADDRESS RANGE

DESCRIPTION

0x0204 6A1C

MDCTL7

Module Control 7 Register (DDR2)

0x0204 6A20

MDCTL8

Module Control 8 Register (HPI)

0x0204 6A24

MDCTL9

Module Control 9 Register (VLYNQ)

0x0204 6A28

MDCTL10

Module Control 10 Register (GPIO)

0x0204 6A2C

MDCTL11

Module Control 11 Register (TIMER 0)

0x0204 6A30

MDCTL12

Module Control 12 Register (TIMER 1)

0x0204 6A34

–

Reserved

0x0204 6A38

–

Reserved

0x0204 6A3C

–

Reserved

0x0204 6A40

–

Reserved

0x0204 6A44

MDCTL17

Module Control 17 Register (SPI)

0x0204 6A48

MDCTL18

Module Control 18 Register (I2C)

0x0204 6A4C

MDCTL19

Module Control 19 Register (PCI)

0x0204 6A50

MDCTL20

Module Control 20 Register (Video Port 0)

0x0204 6A54

MDCTL21

Module Control 21 Register (Video Port 1)

0x0204 6A58

MDCTL22

Module Control 22 Register (Video Port 2)

0x0204 6A5C

MDCTL23

Module Control 23 Register (Video Port 3)

0x0204 6A60

MDCTL24

Module Control 24 Register (Video Port 4)

0x0204 6A64

MDCTL25

Module Control 25 Register (EMIFA)

0x0204 6A68

MDCTL26

Module Control 26 Register (TIMER 2)

0x0204 6A6C

MDCTL27

Module Control 27 Register (TIMER 3)

0x0204 6A70

MDCTL28

Module Control 28 Register (VIC)

0x0204 6A74

MDCTL29

Module Control 29 Register (McASP)

0x0204 6A78

MDCTL30

Module Control 30 Register (UART)

0x0204 6A7C

MDCTL31

Module Control 31 Register (VICP)

0x0204 6A80

–

Reserved

0x0204 6A84

MDCTL33

Module Control 33 Register (C64x+ CPU)

0x0204 6A8C

MDCTL34

Module Control 34 Register (Ethernet Subsystem)

0x0204 6A90- 0x0204 6FFF

–

Reserved

The DM647/DM648 includes two power domains: the System Domain and the Ethernet Subsystem

Domain. Both of these power domains are always on when the chip is on. Both of these domains are

The primary PLL controller generates the input clock to the C64x+ megamodule as well as most of the

system peripherals such as the multichannel audio serial ports (McASPs) and the external memory

interface (EMIFA). The secondary PLL controller generates interface clocks for the DDR2 memory

controller. The Ethernet Subsystem is clocked through the SerDes module, which takes input from

REFCLKP/N. The primary PLL controller (PLL1 controller) uses the device input clock CLKIN1 and the

secondary PLL controller (PLL2 controller) uses the device input clock CLKIN2

Table 6-4 provides a listing of the DM647/DM648 clock domains.

Table 6-4. DM647/DM648 Power and Clock Domains

POWER DOMAIN

CLOCK DOMAIN

PERIPHERAL/MODULE/USAGE

System Domain

CLKDIV1

C64x+ CPU

System Domain

CLKDIV3

EDMA/SCR

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