TMS320DM647 datasheet(49/166 Pages) TI

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System Interconnect

4.1 Internal Buses, Bridges, and Switch Fabrics

4.2 Data Switch Fabric Connections

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

On the DM647/DM648 devices, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system

peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency,

concurrent data transfers between master peripherals and slave peripherals. Through a switch fabric, the

CPU can send data to the video ports without affecting a data transfer between the PCI and the DDR2

memory controller. The switch fabrics also allow for seamless arbitration between the system masters

when accessing system slaves.

Two types of buses exist in the DM647/DM648 devices: data buses and configuration buses. Some

DM647/DM648 peripherals have both a data bus and a configuration bus interface, while others only have

one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.

Configuration buses are mainly used to access the register space of a peripheral and the data buses are

used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer

data. For example, data is transferred to the UART or I2C via their configuration bus. Similarly, the data

bus can also be used to access the register space of a peripheral. For example, the EMIFA and DDR2

memory controller registers are accessed through their data bus interface.

The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be

classified into two categories: masters and slaves. Masters are capable of initiating read and write

transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand,

rely on the EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers

and PCI. Slaves include the McASP, video port, and I2C.

The DM647/DM648 devices contain two switch fabrics through which masters and slaves communicate.

The data switch fabric, known as the data switched central resource (SCR), is a high-throughput

interconnect mainly used to move data across the system (for more information, see Section 4.2). The

data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK2 frequency (SYSCLK2

is generated from PLL1 controller). Peripherals that have a 128-bit data bus interface running at this

speed can connect directly to the data SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly

used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3).

The configuration SCR connects C64x+ Megamodule to slaves via 32-bit configuration buses running at a

SYSCLK2 frequency (SYSCLK2 is generated from PLL1 controller). As with the data SCR, some

peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also

connects to the configuration SCR. Bridges perform a variety of functions:

• Conversion between configuration bus and data bus.

• Width conversion between peripheral bus width and SCR bus width

• Frequency conversion between peripheral bus frequency and SCR bus frequency

For example, the EMIFA memory controller require a bridge to convert their 64-bit data bus interface into a

128-bit interface so that they can connect to the data SCR.

Note that some peripherals can be accessed through the data SCR and also through the configuration

SCR.

Figure 4-1 shows the connection between slaves and masters through the data switched central resource

(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves

via 128-bit data buses running at a SYSCLK2 frequency. SYSCLK2 is supplied by the PLL1 controller and

is fixed at a frequency equal to the CPU frequency divided by 3. Some peripherals, like PCI and the

C64x+ Megamodule, have both slave and master ports. Note that each EDMA3 transfer controller has an

independent connection to the data SCR.

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