MBM29PL65LM90TN datasheet(26/56 Pages) SPANSION

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MBM29PL65LM-90/10

If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to

determine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase

cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the

command has been accepted, the system software should check the status of DQ3 prior to and following each

subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have

been accepted.

See “Hardware Sequence Flags”.

DQ2

Toggle Bit II

This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase

suspended sector will indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows :

For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status” and "DQ2 vs DQ6".

Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles

if this bit is read from an erasing sector.

Reading Toggle Bits DQ6/DQ2

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit

after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ7 to DQ0 on the following read cycle.

However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system

also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then

determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5

went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, deter-

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the

status of the operation. Refer to “Toggle Bit Algorithm”.

MBM29PL65LM90TN Datasheet(PDF) 26 Page - SPANSION