MBM29PL65LM90TN datasheet(20/56 Pages) SPANSION

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MBM29PL65LM-90/10

mand sequence, the system is not required to provide further controls or timings. The device will automatically

provide adequate internally generated program pulses and verify the programmed cell margin.

DQ7(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be moni-

tored to determine the device status during Write Buffer Programming. In addition to these functions, it is also

possible to indicate to the host system that Write Buffer Programming Operations are either in progress or have

been completed by RY/BY. See “Hardware Sequence Flags”.The Data polling techniques described in “Data

Polling Algorithm” in s FLOW CHART should be used while monitoring the last address location loaded into the

write buffer. In addition, it is not neccessary to specify an address in Toggle Bit techniques described in “Toggle

Bit Algorithm” in s FLOW CHART. The automatic programing operation is completed when the data on DQ7 is

equivalent to the data written to this bit at which time the device returns to the read mode and addresses are

no longer latched ( See "Hardware Sequence Flags").

The write-buffer programming operation can be suspended using the standard program suspend/resume com-

mands.

Once the write buffer programming is set, the system must then write the “Program Buffer to Flash” command

at the Sector Address. Any other address/data combination will abort the Write Buffer Programming operation

and the device will continue busy state.

The Write Buffer Programming Sequence can be ABORTED by doing the following :

• Different Sector Address is asserted.

• Write data other than the “Program Buffer to Flash" command after the specified number of “data load” cycles.

A “Write-to-Buffer-Abort Reset” command sequence must be written to the device to return to read mode. (See

“MBM29PL65LM Standard Command Definitions” in s DEVICE BUS OPERATION for details on this command

sequence.)

Chip Erase Command

Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm

command sequence the device automatically programs and verifies the entire memory for an all zero data pattern

prior to electrical erase. (Preprogram Function) The system is not required to provide any controls or timings

during these operations.

The system can determine the erase operation status by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The chip

erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and

terminates when the data on DQ7 is “1” at which the device returns to read the mode.

Chip Erase Time: Sector Erase Time

× All sectors + Chip Program Time (Preprogramming)

Refer to "Embedded EraseTM Algorithm" for typical command strings and bus operations.

Sector Erase Command

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

starts later, while the command (Data = 30h) is latched on the rising edge of CE or WE whichever states first.

After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin.

Multiple sectors are erased concurrently by writing the six bus cycle operations on "MBM29XL12DF Command

Definitions Table" in s DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase

command to addresses in other sectors desired to be concurrently erased. The time between writes must be

less than “tTOW” otherwise that command is not accepted and erasure does not start. It is recommended that

processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled

after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever

starts first initiates the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever

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