MBM29PL65LM90TN datasheet(25/56 Pages) SPANSION

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MBM29PL65LM-90/10

Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change

asynchronously while the output enable (OE) is asserted low. This means that device is driving status information

on DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples

the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm

operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to

DQ7 will be read on successive read attempts.

The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm

or sector erase time-out. See “Toggle Bit Status” and “Data Polling during Embedded Algorithm Operation Timing

Diagram”.

DQ6

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the

busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse

sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse

in the six write pulse sequences. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written is protected, the toggle bit will toggle for about 1

µs and then stop

toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If

all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into

read mode, having data kept remained.

Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause

DQ6 to toggle.

The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank

is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the

Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6

to toggle. See “AC Wavefrom for Toggle Bit I during Embedded Algorithm Operations”.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under

these conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle was

not successfully completed. Data Polling is only operating function of the device under this condition. The CE

circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins

will control the output disable functions as described in "MBM29PL65LM User Bus Operations Table (DW/W

VIL)" and "MBM29XL12DF User Bus Operations Table (DW/W

= VIH)" in s DEVICE BUS OPERATION.

The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In

this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.

If this occurs, reset device with the command sequence.

DQ3

Sector Erase Timer

After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain

low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command

sequence.

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