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MBM29PL65LM90TN Datasheet(PDF) 18 Page - SPANSION

Part # MBM29PL65LM90TN
Description  FLASH MEMORY CMOS 64 M (4M X 16) BIT MirrorFlashTM
PDF  56 Pages
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MBM29PL65LM-90/10
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s COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
"MBM29PL65LM Command Definitions Table" in s DEVICE BUS OPERATION shows the valid register com-
mand sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while
the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) com-
mands are valid only while the Program operation is in progress. Moreover, Read/Reset commands are func-
tionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7
to DQ0 and DQ15 to DQ8 bits are ignored.
Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Reset mode, verify mode of
secter protect commands, the Read/Reset operation is initiated by writing the Read/Reset command sequence
into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains
enabled for reads until the command register contents are altered.
The device automatically powers-up in the Read/Reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles retrieve array data. This default value ensures that no spurious
alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and
Waveforms for specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore
manufacture and device codes must be accessible while the device resides in the target system. PROM pro-
grammers typically access the signature codes by raising A9 to a higher voltage. However multiplexing high
voltage onto the address lines is not generally desired system design practice.
he device contains Autoselect command operation to supplement traditional PROM programming methodology.
The operation is initiated by writing the Autoselect command sequence into the command register.
This is followed by a third write cycle that contains the address and the Autoselect command. Then the manu-
facture and device codes can be read from the address, and an actual data of memory cell can be read from
the another address.
Following the command write, a read cycle from address 00h returns the manufacturer’s code (Fujitsu=04h).
And, at double word mode, a read cycle at address 01h outputs device code. At word mode, 227Eh is output,
this indicates that two additional codes, called Extended Device Codes will be required. Therefore the system
may continue reading out these Extended Device Codes at the address of 0Eh, as well as at (BA) 0Fh (at word
mode, 1Eh). Refer to "MBM29PL65LX Autoselect Codes Table" in s DEVICE BUS OPERATION.
To terminate the operation, it is necessary to write the Reset command sequence into the register. To execute
the Autoselect command during the operation, Reset command sequence must be written before the Autoselect
command.
Program Command
The device is programmed on word-by-word basis (or double word-by-double word). Programming is a four bus
cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and
data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data
is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the
system is not required to provide further controls or timings. The device automatically provides adequate inter-
nally generated program pulses and verify programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or
RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed.



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