SRC4382IPFBT datasheet(54/85 Pages) TI2

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SRC4382

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

This bit is used to mute the Port B audio data output.

BMUTE

Output Mute

Disabled; SDOUTB is driven by the output data source. (Default)

Enabled; SDOUTB is forced low.

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

BCLK1

BCLK0

BDIV1

BDIV0

BDIV[1:0]

Port B Master Mode Clock Divider

These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation.

BCKB is always set to 64 times the LRCKB clock rate in Master mode.

BDIV1

BDIV0

Master Mode Clock Divider

Divide By 128 (Default)

Divide By 256

Divide By 384

Divide By 512

BCLK[1:0]

Port B Master Clock Source

These bits are used to set the master clock source for Port B when configured for Master mode operation.

BCLK1

BCLK0

Master Clock Source

MCLK (Default)

RXCKI

RXCKO

Reserved

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

TXCLK

TXDIV1

TXDIV0

TXIS1

TXIS0

BLSM

VALID

BSSL

Block Start or Asynchronous Data Slip Interrupt Trigger Selection

This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit.

BSSL

TSLIP Interrupt Trigger Source

Data Slip Condition (Default)

Block Start Condition

VALID

Validity (V) Data Bit

This bit may be used to set the validity (or V) data bit in the AES3-encoded output. Refer to the VALSEL bit in control register 0x09 for

V-bit source selection.

VALID

Transmitted Validity (V) Bit Data

Indicates that the transmitted audio data is suitable for conversion to an analog signal or for further digital

processing. (Default)

Indicates that the transmitted audio data is not suitable for conversion to an analog signal or for further

digital processing.

BLSM

Transmitter Block Start Input/Output Mode

This bit is used to select the input/output mode for the DIT block start pin, BLS (pin 35).

BLSM

BLS Pin Mode

Input (Default)

Output

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