SRC4382IPFBT datasheet(11/85 Pages) TI2

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SRC4382

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

PIN DESCRIPTIONS (continued)

NAME

PIN NUMBER

I/O

DESCRIPTION

INT

Output

Interrupt Flag (open-drain, active Low)

RST

Input

Reset (active Low)

MCLK

Input

Master Clock

GPO1

Output

General-Purpose Output 1

GPO2

Output

General-Purpose Output 2

GPO3

Output

General-Purpose Output 3

GPO4

Output

General-Purpose Output 4

DGND2

Ground

DIR Line Receiver Bias and DIT Line Driver Digital Ground

TX–

Output

DIT Line Driver Inverting Output

TX+

Output

DIT Line Driver Noninverting Output

VDD33

Power

DIR Line Receiver Bias and DIT Line Driver Supply, +3.3V Nominal

AESOUT

Output

DIT Buffered AES3-Encoded Data

BLS

I/O

DIT Block Start Clock

SYNC

Output

DIT internal Sync Clock

BCKA

I/O

Audio Serial Port A Bit Clock

LRCKA

I/O

Audio Serial Port A Left/Right Clock

SDINA

Input

Audio Serial Port A Data Input

SDOUTA

Output

Audio Serial Port A Data Output

—

No Internal Signal Connection, Internally Bonded to ESD Pad

VIO

Power

Logic I/O Supply, +1.65V to +3.6V

DGND3

Ground

Logic I/O Ground

BGND

Ground

Substrate Ground, Connect to AGND (pin 10)

SDOUTB

Output

Audio Serial Port B Data Output

SDINB

Input

Audio Serial Port B Data Input

LRCKB

I/O

Audio Serial Port B Left/Right Clock

BCKB

I/O

Audio Serial Port B Bit Clock

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