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SRC4382IPFBT Datasheet(PDF) 65 Page - Texas Instruments |
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SRC4382IPFBT Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 85 page  www.ti.com SRC4382 SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007 Register 1B: General-Purpose Output 1 (GPO1) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO13 GPO12 GPO11 GPO10 GPO[13:10] General-Purpose Output 1 (GPO1) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO1. GPO13 GPO12 GPO11 GPO10 GPO1 Function 0 0 0 0 GPO1 is Forced Low (Default) 0 0 0 1 GPO1 is Forced High 0 0 1 0 SRC Interrupt, Active Low 0 0 1 1 Transmitter Interrupt, Active Low 0 1 0 0 Receiver Interrupt, Active Low 0 1 0 1 Receiver 50/15 μs Pre-Emphasis, Active Low 0 1 1 0 Receiver Non-Audio Data, Active High 0 1 1 1 Receiver Non-Valid Data, Active High 1 0 0 0 Receiver Channel Status Bit 1 0 0 1 Receiver User Data Bit 1 0 1 0 Receiver Block Start Clock Receiver COPY Bit 1 0 1 1 (0 = Copyright Asserted, 1 = Copyright Not Asserted) Receiver L-Bit 1 1 0 0 (0 = First Generation or Higher, 1 = Original) 1 1 0 1 Receiver Parity Error, Active High 1 1 1 0 Receiver Internal Sync Clock 1 1 1 1 Transmitter Internal Sync Clock Register 1C: General-Purpose Output 2 (GPO2) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO23 GPO22 GPO21 GPO20 GPO[23:20] General-Purpose Output 2 (GPO2) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO2. GPO23 GPO22 GPO21 GPO20 GPO2 Function 0 0 0 0 GPO2 is Forced Low (Default) 0 0 0 1 GPO2 is Forced High 0 0 1 0 SRC Interrupt, Active Low 0 0 1 1 Transmitter Interrupt, Active Low 0 1 0 0 Receiver Interrupt, Active Low 0 1 0 1 Receiver 50/15 μs Pre-Emphasis, Active Low 0 1 1 0 Receiver Non-Audio Data, Active High 0 1 1 1 Receiver Non-Valid Data, Active High 1 0 0 0 Receiver Channel Status Bit 1 0 0 1 Receiver User Data Bit 1 0 1 0 Receiver Block Start Clock Receiver COPY Bit 1 0 1 1 (0 = Copyright Asserted, 1 = Copyright Not Asserted) Receiver L-Bit 1 1 0 0 (0 = First Generation or Higher, 1 = Original) 1 1 0 1 Receiver Parity Error, Active High 1 1 1 0 Receiver Internal Sync Clock 1 1 1 1 Transmitter Internal Sync Clock Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 65 Product Folder Link(s): SRC4382 |
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