TAS2020 datasheet(21/79 Pages) TI2

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The digital voltage control registers DVC_LEVEL and DVC_SLEW_RATE registers can be configured using the

PPC3 Software Section 6.4.1.

Table 6-14. Digital Volume Control

DVC_LEVEL[23:0]

VOLUME (dB)

0x000000

Software MUTE

0x00000D (MIN)

-110

...

0x400000

0 (default)

...

0x7FB261 (MAX)

Table 6-15. Digital Volume Ramp Rate

DVC_SLEW_RATE[23:0]

RAMP RATE @ 48kHz (s)

0x00036A

1000ms

...

0x034A51

4ms (default)

...

0x7FFFFF

0 - Ramp disabled

6.4.2.2 High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The playback path

employs a high-pass filter (HPF) to prevent this from occurring. The HPF is a 1st order filter and can be changed

from the default 2Hz for 48ksps fs using the AUDIO_HPF_N0, AUDIO_HPF_N1, AUDIO_HPF_D1 registers. The

HPF filter frequency scales with change in the FSYNC clock and can be re-configured to achieve the required

cutoff frequency for different FSYNC clock frequencies. The coefficients can also be changed to disable the HPF

coefficients appropriately. These coefficients should be calculated and set using PPC3 Software Section 6.4.1.

6.4.2.3 Class-D Amplifier

TAS2020 has integrated high performance class-D amplifier with low idle channel noise, low distortion and high

PSRR. The Class-D amplifier switches on a clock frequency derived from the SBCLK frequency and is always

synchronized to the input clock source. The SAMP_RATE_CFG register enables selection between input clock

source based out of multiple of 44.1kHz vs 48kHz multiples.

Table 6-16. Sample rate configuration

SAMP_RATE_CFG

Configuration

0 (default)

Audio data rate is multiple/sub-

multiple of 48ksps

Audio data rate is multiple/sub-

multiple of 44.1ksps

For improvements in EMI performance the class-D amplifier supports programmable Edge rate control (ERC)

and class-D clock spread spectrum modulation (SSM).

The edge rate of class-D can be controlled using CLASSD_OUTPUT_EDGERATE_CTRL[1:0] register. By

default the class-D output edge rate is configured to fastest setting to enable high efficiency in the system.

The class-D output edge rate can be slowed down using other configuration settings to reduce the EMI energy

at high frequency with reduction in efficiency. The exact rate of change of output edge rate varies based on

output load conditions, and the values mentioned in the tables below are approximate edge rate levels for default

loading conditions.

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TAS2020

SLASFD4A – AUGUST 2024 – REVISED JULY 2026

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